Smart Home Control and Security

Powerful, Low Power FPGAs Enable Next Generation Smart Home Devices and Appliances

Smart home devices are becoming an attractive option for controlling and monitoring smart homes. Users are increasingly adopting a number of smart home devices from security cameras, smart doorbells to home assistance devices and smart appliances. Designers are looking for flexibility in sensor choices, powerful low power edge processors, and ability to aggregate data from multiple sensors for local or cloud processing.

Lattice’s smart home solutions running on optimized low power FPGAs provide:

  • Low power on-device AI for object detection, identification, counting and Human-machine interface
  • Flexible and low latency sensor data aggregation, bridging and buffering from a wide variety of sensors
  • Programmable I/O expansion and aggregation to solves form factors and architectures challenges

Jump to

Block Diagram

Home Control and Security

Example Use Cases

AI Processing

  • Low Power on-device NN based processing
  • Reduced data traffic to the cloud, improving security, privacy and reducing bandwidth usage
  • Object detection, classification, counting and HMI

Audio Bridging

  • Connect up to 8 microphones to a processor
  • Audio data buffering to offload the processor
  • Support I2S, PDM microphone interfacing
  • Up to 1 Mb of on device RAM for buffering

Image Sensor Bridging

  • Connect a wide variety of image sensors to processors
  • MIPI PHYs supports up to 2.5 Gbps/lane, up to four lanes
  • Flexible host interfacing including CSI, SPI, PCIe
  • Flexible processing for video data muxing and stitching 

Sensor Fusion

  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering
  • Create programmable sensor fusion algorithms

Low Latency Sensor Bridging

  • Take advantage of parallel FPGA architecture to simultaneously collect data from multiple sensors
  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering

Reference Designs

Key Phrase Detection

Reference Design

Key Phrase Detection

Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
Key Phrase Detection
Human Face Identification

Reference Design

Human Face Identification

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification
Human Presence Detection

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
Human Presence Detection
Object Counting

Reference Design

Object Counting

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
Object Counting

Demos

Key Phrase Detection

Demo

Key Phrase Detection

Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
Key Phrase Detection
4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

Demo

Human Counting

Demo

Human Counting

Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
Human Counting
Human Face Detection

Demo

Human Face Detection

Uses Lattice sensAI IP to detect human faces on a tiny, low-power iCE40 UltraPlus FPGA implementing AI at the edge. Adaptable to detect other objects.
Human Face Detection
Human Face Identification

Demo

Human Face Identification

Register and identify faces without retraining, eliminating the need for uploading images and lengthy retraining using a GPU.
Human Face Identification

IP Cores

CNN Accelerator IP

IP Core

CNN Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Accelerator IP
CNN Compact Accelerator IP

IP Core

CNN Compact Accelerator IP

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
CNN Compact Accelerator IP
CNN Plus Accelerator IP

IP Core

CNN Plus Accelerator IP

Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Plus Accelerator IP
CSI-2/DSI D-PHY Receiver

IP Core

CSI-2/DSI D-PHY Receiver

Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
CSI-2/DSI D-PHY Receiver

Development Kits & Boards

Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
CrossLink-NX Evaluation Board

Board

CrossLink-NX Evaluation Board

For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
CrossLink-NX Evaluation Board
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield
CrossLink: LIF-MD6000 – Master Link Board

Board

Support

Quality & Reliability

Reference Material to Help Answer Your Questions

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